Example embodiments of the inventive concept relate to a memory management unit, and more particularly, to a memory management unit which is separately used for each of a plurality of working sets when an intellectual property (IP) operates on the working sets, systems including the same, and a method of operating the same.
A memory management unit (MMU) may be a hardware component that processes a memory access request issued by direct memory access units such as a central processing unit (CPU) and a graphics processing unit (GPU). The MMU may be referred to as a paged MMU (PMMU).
An IP using virtual memory may access a memory device using a physical address corresponding to a virtual address. At this time, the MMU may translate the virtual address into the physical address.
A system on chip (SoC) may operate with a translation lookaside buffer (TLB) in limited size according to a predetermined page replacement policy in order to increase the area efficiency of the MMU and to increase address translation speed. However, when the SoC operates on a plurality of working sets, an IP may refer to a different address space for each of the working sets. Therefore, when only one MMU is used, a working set using the IP changes, which may result in the decrease of the hit ratio of the TLB.